Low Power 0.18um CMOS Phase Frequency Detector
نویسنده
چکیده
In this paper, the performance of two low power phase frequency detectors is compared. A modified D-FF based PFD reduces the power consumption of traditional PFD to 4.732uW at 40MHz clock frequency and dead zone to 40ps.It is suitable for low power applications. A Falling Edge PFD uses only 12 transistors. This PFD operates up to 1GHz at 1.8V supply voltage. It consumes only 5.5uW when operating at 10MHz clock frequency. It has free dead zone. It is seen that FE-PFD is more suitable for low jitter, high frequency applications. Both the circuits are designed and simulated using Tanner13.0v in 0.18um cmos process with 1.8V supply voltage.
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